`timescale 1ms / 100ns

module tb_seg7 ();

reg clk;
reg rst_n;
reg set;
reg [3:0] seg_in;
reg [1:0] anode_in;

wire [3:0] anode_out;
wire [6:0] seg_out;

integer i;

always #1 clk = ~clk;

initial begin
  $vcdpluson(tb_seg7);
end

initial begin
  $monitor("%d : %b | %b >>> [%d] [%b]", i,anode_in, seg_in, anode_out, seg_out);
  clk = 1'b0;
  rst_n = 1'b0;
  set = 1'b0;
  seg_in = 4'b0;
  anode_in = 4'b0;

  @(posedge clk);
  @(posedge clk);
  rst_n = 1'b1;

  for (i = 32'b0; i < 32'd64; i = i + 1) begin
    @(negedge clk);
    {anode_in, seg_in} = i[6:0];
    set = 1'b1;
    @(negedge clk);
    set = 1'b0;
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
    @(negedge clk);
  end

  $finish;
end

seg7_top i_seg7_top (
  .clk(clk),
  .rst_n(rst_n),
  .set(set),
  .seg_in(seg_in),
  .anode_in(anode_in),
  .anode_out(anode_out),
  .seg_out(seg_out)
);

endmodule
